1. Field of the Invention
The present invention relates to a bipolar transistor.
2. Description of the Related Art
Bipolar transistors are generally constructed from two pn junctions lying close together in a semiconductor crystal. In this case, either two n-doped regions are separated from one another by a p-doped region (npn transistors) or two p-doped regions by an n-doped region (pnp transistors). The three differently doped regions are referred to as emitter (E), base (B) and collector (C). Bipolar transistors are well known and are used in diverse ways. In the case of bipolar transistors, a distinction is made between xe2x80x9cindividualxe2x80x9d transistors, which are intended for mounting on printed circuit boards and are accommodated in a dedicated housing, and xe2x80x9cintegratedxe2x80x9d transistors, which are fabricated together with further semiconductor components on a common semiconductor carrier, generally referred to as xe2x80x9csubstratexe2x80x9d.
In addition to the transition frequency of the bipolar transistor, which is one of its limiting frequencies, the base resistance and the base-collector capacitance are critical transistor parameters which determine important characteristic quantities such as the maximum oscillation frequency, the power gain, the minimum noise figure, the gate delay times and the like.
Thus, for example, the following holds true to an approximation:       f    max    =                    f        T                              8          π                xc3x97                  R          B                xc3x97                  C          BC                    
where fmax designates the maximum oscillation frequency, fT designates the transition frequency, RB designates the base resistance and CBC designates the base-collector capacitance.
The transition frequency is essentially determined by the dopant profile in the active transistor region. By contrast, the product RB*CBC can be influenced by the transistor layout (i.e., the geometrical construction).
In the case of previously known bipolar transistors, for example so-called silicon microwave transistors, generally a transistor layout as illustrated diagrammatically in FIG. 1 is used. Such bipolar transistors have at least one emitter formed from one or more emitter elements, one or more base contact(s) and one or more collector contact(s). In this case, the at least one emitter, the at least one base contact and the at least one collector contact are provided in a specific arrangement with respect to one another for the formation of the transistor layout.
As is illustrated in FIG. 1, the emitter (E) can be embodied in strip form, the emitter strip width being given by the minimum possible lithography width. This leads to a smallest possible internal base bulk resistance. In order to minimize the total base resistance, each emitter strip is surrounded by two base connection strips (B). Two emitter strips are usually used, so that only three (instead of four) base strips are required, since the middle base contact can be used for both emitter strips. The collector contacts (C) are embodied beside the outer base contacts.
The transistor layout described can yield the minimum possible resistance for a given minimum lithography width.
The base resistance can be reduced by lengthening the emitter strips, since the base resistance RB is proportional to 1/Ixcex5, where Ixcex5 is equal to the emitter length. It is the case, however, that the base-collector capacitance CBC is proportional to the emitter length Ixcex5, so that the product RB*CBC is to a first approximation independent of the emitter length Ixcex5.
In the case of the known bipolar transistors, the total emitter area is chosen in such a way as to produce the current respectively desired in the application of the bipolar transistors.
Such known bipolar transistors can be used for example for the xe2x80x9cself-aligned dual polysilicon technologyxe2x80x9d.
Taking the known prior art as a departure point, the present invention is based on the object of providing a bipolar transistor which, with regard to its transistor parameters, has an optimized transistor layout in relation to the known solutions.
This object is achieved according to the invention by means of a bipolar transistor, having at least one emitter formed from one or more emitter elements, having one or more base contact(s) and having one or more collector contact(s), the at least one emitter, the at least one base contact and the at least one collector contact being provided in a specific arrangement with respect to one another for the formation of the transistor layout. According to the invention, the bipolar transistor is characterized in that the emitter has at least one closed emitter configuration, in that the at least one emitter configuration bounds at least one emitter inner space, in that two or more base contacts are provided, in that at least one of the base contacts is arranged in the emitter inner space, and in that the at least one other base contact and also the at least one collector contact are arranged outside the emitter configuration.
In this way, it is possible to obtain an optimized transistor construction which, given the same design rules (i.e., the same requirements made of the technology generation), enables a significantly smaller product RB*CBC than in the case of the transistor layouts customarily used previously, as are illustrated in FIG. 1, for example, and described further above. As a result, the properties of the bipolar transistor are improved. In particular, by virtue of the bipolar transistor according to the invention, significantly improved RF (radio frequency) properties of these transistors can be made possible, such as higher transition and maximum oscillation frequencies and a smaller noise figure.
An important difference of the bipolar transistor according to the invention in comparison with the bipolar transistors known in the prior art is that a solution for the minimum base resistance RB is not chosen, but rather that the product RB*CBC is optimized in a targeted manner. Although, as will be explained in greater detail below, this can lead to slightly higher values for RB, distinctly lower values are nonetheless achieved for the base-collector capacitance CBC.
In contrast to the previously known transistor layout, the inventive emitter is embodied in such a way that it has at least one closed emitter configuration. This means that the emitter has at least one continuous component, this continuous component bounding or surrounding at least one emitter inner space. At least one base contact may be situated within this emitter inner space.
The invention is not restricted to specific configurational forms for the emitter configuration according to the invention. A number of non-exclusive exemplary embodiments are explained in more detail in connection with the description of the figures.
Preferred embodiments of the bipolar transistor according to the invention are described below.
The emitter configuration may advantageously have two or more emitter elements which are connected to one another to form the closed emitter configuration.
To that end, the emitter configuration may, for example, have two or more strip-type emitter elements which are oriented in parallel and spaced apart with respect to one another. Furthermore, the strip-type emitter elements may be connected to one another at their free ends in each case via an emitter element formed as an outer emitter web. If more than two strip-type emitter elements are used for the emitter configuration, the outer emitter web may comprise a corresponding number of individual constituent parts, the totality of which then forms the outer emitter web. In contrast to the known transistor layout, the emitter is now no longer embodied only in strip form, rather the two emitter strips are connected by intermediate webs.
In a further refinement, at least one further, inner emitter web which connects the two strip-type emitter elements may be provided between the two outer emitter webs, via which inner emitter web the emitter inner space is subdivided into two or more partial spaces. In such a refinement, with the use of only a single inner emitter web, the emitter configuration thus diagrammatically has the form of an xe2x80x9ceightxe2x80x9d in plan view. The invention is not limited to a specific number of inner emitter webs. When a plurality of strip-type emitter elements are used, the inner emitter web(s) can in turn be formed from a corresponding number of emitter web constituent parts.
Base contacts may in each case be placed between the individual emitter webs. This means that these base contacts may advantageously be arranged in one or more of the partial spaces.
The length of the outer and optionally the inner emitter websxe2x80x94and thus the distance between the strip-type emitter elementsxe2x80x94is preferably chosen to be as small as is allowed by the design rules for the minimum possible size of the base contacts.
The emitter may preferably have two or more closed emitter configurations.
In an advantageous manner, at least two strip-type base contacts and/or two strip-type collector contacts may be provided outside the emitter configuration.
The strip-type base contacts may be oriented parallel and spaced apart with respect to the outer emitter webs.
By contrast, the strip-type collector contacts may be oriented parallel and spaced apart with respect to the strip-type emitter elements.
The advantages of such an orientation of the base contacts and/or collector contacts are explained in more detail below.
The at least one emitter may preferably be connected or be able to be connected in a first metalization plane.
In a further refinement, the at least one base contact may be led or be able to be led into a second metalization plane lying parallel and spatially spaced apart relative to the first metalization plane.
This will be illustrated using an example. If the emitter is connected in the first metalization plane, for example, the base contacts can be led upward into the second metalization plane and, in the latter, then be led via the emitter webs to the respective contact regions at the top and bottom. The use of two such wiring planes does not constitute an additional outlay in comparison with the known bipolar transistor types, because in the latter, too, two metalization planes are required in order to make contact with the emitter, the base and the collector and in order to produce a connection to the so-called bonding pads.
The base connection may preferably be effected between the at least one emitter and the at least one collector contact via a base polysilicon material. Such a base connection has the function of the control electrode in the bipolar transistor. The base connection can control the current from the emitter to the collector, this current being referred to as the transfer current. In the bipolar transistor configuration according to the invention, a dedicated base contact is no longer present between the emitter and the at least one collector contact, in contrast to what was the case in the bipolar transistor types known from the prior art. On the side between the emitter and the collector contact, the base connection is therefore now effected via the base polysilicon material.
This material may particularly advantageously be embodied as silicide. The bipolar transistor can thus be embodied in a particularly efficient manner. With the use of silicide, the sheet resistance is so low in comparison with polysilicon that a low-resistance base connection can be realized between emitter and collector contact even without a close metal contact.
In comparison with the previously known transistor design (see FIG. 1) with an emitter area of the same size (i.e., with the same current yield) the bipolar transistor according to the invention leads to a significantly more compact arrangement and thus to a significantly smaller base-collector capacitance CBC. Moreover, the collector resistance RC is significantly reduced, because the emitter and collector contact are no longer separated from one another by a base contact. With the same design rules, the transistor area can be reduced by about 40% through the layout optimization.
In order to appraise the influence of the implemented layout measure in the bipolar transistor according to the invention on the base resistance RB and the base-collector capacitance CBC, various simulation tests were carried out. The results of these simulations are presented in Table 1 below:
Table 1 shows calculated values for the base resistance RB, the base-collector capacitance CBC and the product RB*CBC. The values were calculated for any transistor design as known from the prior art and a transistor design optimized in accordance with the invention, for a transistor with an emitter mask area of 10 xcexcm2. In Table 1, the results are shown for a configuration known in the prior art, which is designated by xe2x80x9cstandardxe2x80x9d, a configuration known from the prior art with siliconized base polysilicon, which is designated as xe2x80x9cstandard siliconizedxe2x80x9d, an optimized configuration according to the present invention, which is designated as xe2x80x9cnew layoutxe2x80x9d, and a configuration according to the invention with siliconized base polysilicon, which is designated as xe2x80x9cnew layout siliconizedxe2x80x9d.
Without silicide, the use of the bipolar transistor layout according to the invention leads to a reduction of the product value RB*CBC by 27% in comparison with the transistor layout known from the prior art. If silicide is used in each case, the advantage is even greater, with a reduction by 35%.
In summary, the following advantages can be achieved, inter alia, by virtue of the bipolar transistor layout according to the invention. Firstly, the product RB*CBC can be significantly reduced. Furthermore, it is also possible to reduce the collector resistance RC. Moreover, the bipolar transistor according to the invention enables higher transition frequencies, higher maximum oscillation frequencies and smaller noise figures. Furthermore, the collector-substrate capacitance and thus also the power consumption can be reduced. In addition, the bipolar transistors according to the invention need a smaller space requirement, so that more transistors can be fabricated per area, which leads to lower fabrication costs. The advantages that can be obtained can be realized through what is purely a layout measure, so that they are completely cost-neutral. Additional process modules are not necessary. Finally, the bipolar transistors according to the invention are highly universal, i.e., they can be used for all bipolar technologies, thus enveloping a large market volume.
In a particularly advantageous manner, a bipolar transistor according to the invention as described above can be used as a microwave transistor. However, the invention is not restricted to these bipolar transistor types, so that it can also be applied to all other bipolar transistors in integrated circuits.